hw.id, process.pid, time, cgroup/pod attrs, and control-plane artifacts.
Recently added
Deep plans (out of scope today)
1. HIP / ROCm eBPF activity (AMD)
Goal: Parity with CUDA eBPF for AMD — launch counts, grid/block, memcpy, stream sync occupancy estimates — without ROCm app SDK hooks. Approach- Inventory stable userspace symbols in
libamdhip64.so/libhsa-runtime64.so(launch, memcpy, stream sync, set-device). - Reuse the existing uprobe tracer skeleton (
internal/ebpf) with a HIP event ABI parallel to CUDAEventRecord. - Device resolve via
/dev/kfd+ DRM minor → UUID/hw.id(same attr contract as NVML). - Occupancy model: launch→sync thread-seconds clamped to device compute-unit count from sysfs/amdsmi (not DCGM SM fields).
- Soft attach policy: only when AMD GPUs present; missing HIP libs/caps soft-skip (instrument faults still fatal).
2. True GPU completion (vs launch→sync estimates)
Goal: End spans on device completion, not CPU sync return — without CUPTI/app SDK. Options (pick one primary)
Recommended path: A for CUDA when events exist; keep launch→sync as fallback labeled
gpu.measurement.source=ebpf_model; never rename to imply hardware SM occupancy.
Exit criteria: Histogram of gpu.kernel.duration with completion=event|sync_fallback attribute; documented error bars.
3. CUDA Graph per-node kernels
Goal: ExpandcudaGraphLaunch composite span into per-node kernel spans.
Approach
- Uprobe
cudaGraphGetNodes/ instantiate / launch paths; build node-id → kernel-name map at graph instantiate time. - On launch, emit N child spans or N duration samples with
cuda.graph.id+cuda.graph.node_id. - Cardinality: hash node names; cap distinct nodes per process (same budget as kernel-name cap).
- Without stable instantiate hooks: keep composite span (current behavior).
4. cudaStreamWaitEvent / cross-stream edges
Goal: Model wait edges so occupancy does not count blocked wait time as SM-busy.
Approach
- Uprobe wait-event + record-event; store event→stream edges in BPF map.
- Occupancy engine subtracts wait intervals from active thread-seconds.
- Attribute
cuda.wait.eventon duration samples when edge known.
5. Intel GPU util / memory without XPU Manager
Goal: Close Intel util/memory gap using collector-only sources. Approach- Probe
sysfs/hwmon+ DRM fdinfo (already used for process mem). - Optional: dynamic load of Level Zero loader for engine utilization if present (dlopen; soft-skip when missing).
- Document engine util as extension
hw.gpu.engine.utilizationwithgpu.measurement.source=level0.
6. Broader AMD DF / UMC PMU encodings
Goal: Stablehw.cpu.memory.io across EPYC SKUs beyond current uncore_imc* / amd_umc* sysfs discovery.
Approach: Per-family event tables keyed by CPUID; discovery still prefers sysfs; tables fill gaps; self-metric when fallback used.
7. Native Intel PT AUX (no perf binary)
Goal: Capture PT without shelling out to perf record.
Approach: perf_event_open + AUX mmap in internal/intelpt; keep duration/CPU/buffer caps; decode optional/offline. Fail-closed when PT enabled and open fails.
8. Proprietary fleet warehouses
Goal: Not in scope. Export is OTLP (and optional Prometheus). Fleet warehouses / custom backends stay with the customer’s collector pipeline. Collector work: Keep resource identity +hw.id joins solid; no proprietary export protocol.
9. Process-side correlation without an SDK
Goal: Richer join keys without instrumenting apps. Approach (collector-only)- Read
/proc/<pid>/environforTRACEPARENT/OTEL_RESOURCE_ATTRIBUTESwhen present (best-effort, capped). - Join GPU series to cgroup → pod via existing PodResources path.
- Optional: annotate on-demand profile artifacts with pid cmdline + container id only.
Tracked (smaller)
Feature failure policy
Two outcomes at init — never conflated:
TPU scrape endpoint misses and DCGM/RDC blank samples are handled at scrape time (self-metrics), not as startup faults.

